Open Source Hardware
Sometris is a Tetris-like game that Papilio user Peter Ivanov has written for the Papilio One and Arcade MegaWing, the game works with DesignLab 1.0.8.
This is a tetris-like game for Papilio One 500K + Aracade Megawing.
You need a VGA monitor and optionally a Atari/Commodore compatible joystick.
I’ve used Papilio DesignLab 1.0.8.
The source code is available on Github.
Please feel free to comment or reply to the game forum thread.
Hello Papilio fans today we got an awesome project to share with you! Our forum member jlcollado has managed to migrate the Grant Searle’s brillant work called MULTICOMP to the Papilio DUO, the final result is a very usable and complete Z80 soft-core based machine, running the venerable Digital Research CP/M 2.2 OS.
I’ve built the Z80 CP/M variant, complete with VGA & Keyboard terminal, Serial port, SD-Card and external SRAM. The steps I followed to accomplish this:
For an in depth look at this great work please visit the project showcase page here, the full project files are also available on the same page.
Feel free to express your thoughts about the project in the comment section or in the original showcase page.
Hello FPGA and Arcade games fans! A couple of weeks ago we posted about how to play the Snake game on your FPGA in fore easy steps, our community member mkarlsson was not totally satisfied with the amount of FPGA resources the Verilog code uses and decided to rewrite the game to make it use less resources and now it even fits an LX9 based board like Papilio Pro or Duo with a VGA wing:
The GadgetFactory blog page has this story about the snake game written in Verilog so I decided to take a look at it. Sadly to say it’s pretty much a textbook example of how not to write HDL code. However, this idea seemed pretty cool so I decided to do an almost complete rewrite of the code (basically the only thing left from the original code is the VGA controller) while still keeping all the functionality of the original code. The new version uses about a 1/4 of the FPGA resources compared to the original code when compiled for Spartan6 and it now fits an LX9.
Please visit the original forum thread here to share your thoughts about this project.
Source code is available on github.
By mkarlsson.
Hello Papilio fans! Here at Gadget Factory we are happy to announce a so special Cyber Monday discount! This year’s special deal is not like any other deal we made before and here is why:
The Papilio DUO is marked down from $124 to $99 and on top of that you would get a Computing Shield or LogicStart Shield of your choice for free. This is a $160 value for just $99!
This is your best chance to get the DUO for the best price ever while supplies last!
https://youtu.be/N8pwx4Y7E30
There are tons of ways of creating a home-made microcontroller. Today we present a very detailed tutorial on how to achieve this using the rotary encoder from the scroll button of a mouse.
This is part 5 of a series. The goal here is to achieve a constant frequency signal at the output of the Papilio Pro and be able to vary the duty cycle just turning the wheel of the mouse. The other parts of the series would teach how to wire the whole circuitry as well as how to capture the encoder info for the different modules. Have fun!
The first successful flight of a drone, or unmanned air vehicle (UAV) running on ArduPilot was recently announced.
This UAV is powered by a Zynq, a dual-core ARM with an onboard FPGA. This FPGA makes the difference, leaving alone the first flight of a drone using ArduPilot. Using this FPGA allows the controller to handle real-time control tasks including video feeds and flight dynamics much quicker and more efficiently.
The code implemented will be published on the OcPoc project, an open source initiative with Dronecode.
Source: hackaday.com
Hi,
after a few years being forced to play with other targets, I revisited the Papilio One and ported my in-house ‘MaSoCist’ setup to it. Yet another solution, you might think. Well, the motivation was to go minimal, but configureable. The MaSoCist is different in that respect that it rather is an environment than an actual design, however it is powered by the resource-saving ZPU architecture by default. The original Zealot ZPU variant, enhanced with a bit of debug logic, is doing an ok job for configuration, but is wasting quite a few cycles on the dual port RAM I/O and had shortcomings on the interrupt handling side, so I had bashed out a pipelined variant which does things a little differently. It’s been in use as configuration processor or even test bench for more complex logic so far. Logic usage is a little higher than the original Zealot. The full SoC with UART, PWM, Timer, IRQ controller, and simple Cache logic for virtual adressing of a SPI flash takes less than 50% of the Papilio One.
Currently, the CPU is running at 32 MHz only. There’s more in for it, if the memory system and fetch logic is improved (v2, in the making). The v0 and v1 variant of the core run on a three-stage pipeline.
Anyhow, I managed to upload a (crappy) video, moving pictures speak more:
Cheers,
– Martin