Hello FPGA innovators! Remember the arcade obstacle avoidance game where blocks of pixels fall on you and you steer clear of them moving left or right? Today’s project attempts to re engineer the same game using a VGA and FPGA. Here, a pseudo random code is used to generate obstacles that fall down and buttons on the FPGA are used to move the cursor so that none of the obstacles hit it.
The only hardware required to execute this project is an FPGA board (you might need to adapt yours if different from the author’s), a computer monitor and connection cables. This is because the FPGA board has inbuilt push buttons that can be used to move the cursor of the game, and also has the necessary DACs and VGA interfaces required to run the game.
The coding done by the author is in VHDL and everything starting from a functional flowchart to running the bit file for FPGA has been described from steps 1 to 9. Since the buttons on the FPGA has a bouncing issue, a separate debouncer code needs to be run which is available on step 2. Details regarding the VGA, coding for random obstacles and checking for collisions and updating the game are given from steps 3 to 7.
Though the authors put in 50+ hours of effort and made a great attempt, the game still could be done in a lot more simpler ways. The main code is available in the introduction to spare other followers from putting in more additional effort, but starting from choosing a different FPGA board to running through basics of other games implemented using VGA and FPGA can end up delivering something better with a lot less effort.
Greetings FPGA innovators! Stepper motors can be an integral part of projects that have a dimension of mobility to them. Be it rovers, robots, drones or claw machines, controlling stepper motors with joysticks is an integral part and FPGAs accomplish speed control easily. Today’s post is about using a FPGA and a joystick to control stepper motors.
The Hardware required for the project is a FPGA board, 2 PmodSTEP drivers, 1 PmodJSTK, 2 Stepper motors, a USB A to B micro cable and 2 12 pin PMOD cables. Since the author is only focused on the control of the stepper motors, the hardware for this project is limited. However it can be expanded based upon the scale of your endeavour.
The code structure is given by the author in step 2. The author has configured the PmodJSTK interface to receive data and not send data to the LEDs on the board. The working principle is pretty simple, where the decoder works out the signals from the Joystick and sends it to the drivers in the form of electrical signals that make the motors turn left, right, stay still or maintain course. The FPGA acts as a simple interconnect between the drivers. The code has been given in a zip file by the author in step 3.
The coding language used is VHDL and the code is divided into modules. Step 4 has been dedicated to code generation and creation of the executable bit file that can be used on the FPGA. Step 5 illustrates the connections for the project.
Hello FPGA lovers! Today’s post is an interesting one which helps us visualize the audio spectrum with the help of your FPGA and an LED strip. Using a VGA cable, the spectrum can be visualised in a computer monitor as well. The microphone on theFPGA used (you may need to adapt this to your own board) captures the surrounding sounds and uses the FPGA to convert it into a perceivable visual output. The author has explained the principle of working in step 2. The input audio signal is stored in 2 block RAMs. The 1st RAM consists of the time domain representation which is used for display in the VGA. The 2nd RAM consists of the Frequency domain representation using FFT which is displayed both in the VGA and the LED strip.
The Hardware required for this project is a FPGA board, USB A to B micro cable, VGA cable, 30 LED Strip, VGA display (PC monitor) and 3 male to male jumper wires. The author has used the PC monitor as the VGA display for this project. However you can use a dedicated LCD screen or any other VGA display if you choose to. The hardware connections are explained in step 3.
The code is available as a zip file in step 4. The author has dedicated steps 4 and 5 towards installing and generating the program for the board. The language used is VHDL and the code has been broken down into modules. The zip file consists of the source files, a readme file explaining the code, a .tcl file to automatically build the project and the .bit and .bin files for programming the FPGA.
Greetings FPGA innovators! Ever had the problem of forgetting to switch off the room lights on your way out? Do you have frequent guests who are not as mindful as you when it comes to power saving? In today’s project we see how to build a simple gadget with the FPGA to switch off your room lights once there is no one in. Not only will The FPGA trip light save power and work intelligently, but it will also help you cut power costs.
The Hardware needed for the project are a FPGA board (adaptation to your own device might be required), 2 off IR transceiver pairs, 4 off 1000 ohm resistors, 2 off 33 ohm resistors and 2 off 100 ohm resistors besides 2 breadboards and jumper wires. The author has shared details regarding the circuit setup, the FPGA board and the Breadboard connections in step 4. A housing model for the circuit has been shown in step 5 which will help the circuit to be used in a more compact and practical way.
The FPGA has been coded with the VHDL language. The black box diagram for implementing in the FPGA and its descriptions has been given in detail in step 2. The code has been divided into modules and has been given for ready availability in step 3.
The basic operation of the gadget is such that one transceiver pair counts the number of people entering the room, and the other counts the number of people leaving the room. The FPGA acts as a simple comparator and when both the counts are equal, the room lights are turned off.
Hello FPGA enthusiasts! The FPGA is truly a tool that can stretch the horizon of possibility and in today’s project we will find out how an FPGAcan be used as an universal remote control. Ever had the problem of falling asleep while watching TV? Not anymore! The Universal Timed remote with FPGA is a timed remote which can be used to switch off any TV set once the timer ticks down!
The Hardware needed for this project are a FPGA Board, a breadboard, a 300 ohm resistor, male to male connecting wires and an IR LED and Sensor pair besides a TV set to test the device on. The circuit diagram has been given by the author in step 2.
The code has been written using VHDL and the VHDL setup for the FPGA is given in step 3. The code has been subdivided into modules and the whole file has also been attached in step 3 as a zip file. The main modules are the IR control and the Timer, which work in tandem to switch off the TV once the timer counts down.
Future enhancements and possible improvements have also been shared by the author. The timer can be set between 1 hour and 99 hours though it has been designed only to work for your own TV set. But a little bit of tweaking can make this a universal remote too!
Greetings inhabitants of the FPGA world! Today’s post is about a project that can be a huge part of a number of other different projects that use FPGA as their core. Be it a claw machine or a drone or a navigator robot, interfacing Joysticks with FPGA will be a fundamental part of many of your future work. This article will help you control any device on a two dimensional platform with the code for movement in the XY plane. Moving in 3D (flight in the case of drones) can be easily achieved by using two joysticks in place of one.
The Author has wrapped up her project in a set of 5 steps to keep things short and sweet. The hardware needed for this project is simply a FPGA board, a system with Xilinx Vivado installed, Digilent PmodJSTK and a USB A to B micro cable. A general idea regarding the project is given in Step 2. The Joystick uses the SPI interface to receive and transmit data from and to the FPGA board.
The code for this project has been readily supplied in step 3 as a zip file. The contents can be sorted into a number of modules which have been coded in Vivado 2015.4. So using a different version of the software will mean you need to copy paste the codes into a new project file in your system.
The code can then be converted to bit stream to programme the board. You can also programme 2 joysticks (for Drones or RC Cars) since only the top bank of the PMOD Header in the FPGA board (you may need to adapt this to your own board) has been used for 1 joystick.
Hello FPGA hobbyists! Ever wondered what it would be like to see sound? The author thveryat very same curiosity for close to 10 years, and kept a constant vigilance for ideas to build something that would help him materialize his dreams. The Daredevil camera, built using a bunch of MEMS microphones and a FPGA actually lets you see sound.
The author started the project wielding inspiration from the Duga RADAR. However, the scale of the project becomes huge and something beyond what hobbyists can afford. The author then tried a more practical but tedious and time consuming design approach which involved using an array of microphones. Each microphone in the array picks the sound relative to its position and displays it on screen, which will always be different from the next microphone because of the difference in position.
While the logic behind this is sound, implementing an array of microphones, each having a Pre-amp stage and then an ADC stage before feeding inputs to the FPGA is not practical. The cost and time put into the project becomes huge, and even then error margins can be significantly high.
This is the reason why the author used a set of MEMS microphones. MEMS microphones have an inbuilt Pre-amp and ADC stage, and thus the project collapses in complexity. All that is needed is an array of MEMS microphones and an FPGA board to implement the project. FPGAs are FFT friendly and this has a huge part in the project.
The author has shared the PCB design layout here. Besides this a number of fail safes such as spare patterns for a Flash chip, SOIC and DIP. He also used micro SD cards for each array to store the data and send it for processing to get an output of close to 30 frames per second. The FPGA, a great tool for pipelining is used to get his output.
The author then tried out the theory in an 8×8 array and arrived at the conclusions that the device is pretty sensitive as it even picks up sound way reflections from surfaces. But since anechoic chambers are impossible to build at home, he went on to build a 16×16 array.
While the results can be seen in this page, the author is yet to perfect his design. There are persistent issues with micro SD card since its storage algorithm conveniently cuts off data to compress data, which is essential for the FPGA to build a 30 Frame/sec output.
To be heard…or seen.
Greetings FPGA fans! Today’s post takes power generation and conservation to another level! We all know that Solar Panels are an excellent source of non-conventional power. But if the panel is not facing the sun the power generation is never optimum. The sun changes its position continuously and a static solar panel can only generate optimum power for a short window of time when it directly faces the sun. But what if the solar panel too changed its position with respect to the sun? Then we would have a case where the panel generates optimum power for more than 8 hours which is a lot more compared to just the 1-2 hours it does when it is static!
Today’s project aims at making a dynamic solar panel with FPGA. This Dynamic Solar Panel changes its position according to the Sun’s position by making use of a comparator that compares voltage values periodically and rotates the panel. The hardware required for this project are 2 Bidirectional Parallax servo motors, a 9V DC Solar Panel, a FPGA, a Breadboard, A 3D Printed frame and 3 100 Ohm resistors.
The Project basically involves the use of an FSM designed by the author. The design steps have been explained in detail from steps 2 – 8. Any FPGA with sufficient inputs and outputs can be used for this project but the code shared by the author has been programmed for the Basys 3. So unless you’re feeling really adventurous, it would be best to follow what the author has done!
The program has been done in VHDL (.vhd) and is available here. It has been arranged into different modules and each module corresponds to one of the design steps from 2 – 8. The program is pretty easy to follow and improvising it to suit another FPGA board should be easy if you know VHDL.
The wiring has been shared in step 10. The author has used a 3D printed frame whose schematic has been shared in step 11. However if you plan on building your own frame from wood or cardboard, you can refer the sketches.