How To Control What You See On A Screen in Two Hours and For Less Than $25!

Imagine how cool it would be to control what appears on your screen and at a bargain price, just using your FPGA (yes! Your Papilio!) and some other easy-to-get components.

All you need is read today´s article (and buy the tiny things of course). This how-to post is one of those which are written thinking of the user. It explains everything, even the physics that rule the system.

For this specific example, a DAC resistor is connected to the FPGA on a CPLD board so it can output 512 colors to a VGA screen. Knowledge of VHDL is needed in order to implement your own code, otherwise, simply use the one given although you can follow the links on the article to learn some more about VHDL.

The real advantage is that you will be able to implement your own VHDL modules so you will actually control what appears on the screen!

 

Now it´s your time. Show the World what you can do…through a VGA monitor!

 

By Chris

Here is How The Dark Side Got Started With Their Robot Army!

Nowadays, you may be fed up of Star Wars jokes, baits and so on. I am sorry, I could not resist the temptation.

Anyway, this time, at least, was not a joke nor a lie. Today´s article brings the real truth to you. If you want to build your own robot, as simple as you want it to be, the first step should be to learn about controlling a DC motor! Now it does not sound as funny as watching the results achieved by the Dark Side´s Army. You may be wrong because this tutorial is everything but boring.

Very easy to read, this step-by-step article presents all you need to learn to properly understand how to control a DC motor just with your FPGA (yes you can use your Papilio). All you need is outlined and well explained (the code needed is given…). There are also some easy to understand physics explanations so you will get to understand the real ins of this project.

Do not miss this tutorial and be ready to get hired by The Dark Side!

 

By Chris

The Oldland CPU 32-bit FPGA Core

Here is a promising looking Soft Processor core available on OpenCores.com. It looks like it has some nice simulation and debugging tools built in – as well as a C toolchain.

Included with the package is oldland-rtlsim, which lets you simulate the processor on a PC. The oldland-debug tool lets you connect to the processor for programming and debugging over JTAG. Finally, there’s a GNU toolchain port that lets you build C code for the device.

Inferring true dual-port, dual-clock RAMs in Xilinx and Altera FPGAs

Excellent method to infer a Block RAM memory block of any size in simple code that works for Xilinx and Altera devices. I needed to generate some BRAM for a DesignLab module I was putting together and I remembered I had seen this somewhere but couldn’t remember where… Some digging in google brought this back up so I thought I better get this posted to the blog so we can easily find it in the future.

Xilinx_logo_spotALTERA CORPORATION LOGO

I’m a big fan of inference, especially as it applies to writing synthesizable Verilog code for FPGAs. Properly coded, a module that infers technology-dependent blocks (e.g. block RAMs) should: be portable between devices from a particular vendor (e.g. Spartan 3E to Virtex 6), be portable between devices from different vendors (e.g. Spartan 6 to Cyclone III), and even be portable to vendor-independent environments (e.g. simulation in Icarus Verilog).

Stepper

Hamster puts together a nice tutorial with code about driving a stepper motor with an FPGA.

 

 

 

 

 

 

 

Driving a stepper motor using an external driver board is a bit tricky when using a microcontroller. With an FPGA it is a piece of cake!

Intelligent LEDs – Using WS2812B LEDs with the Papilio.

 

Hamster shows us how to use the latest and greatest WS2812B LEDs!

Ws2812b leds.jpg

The interface is pretty simple – the state of the bus has to be reset by holding the data signal low for 50us, followed with sending out 24 bits for each LED that is connected in the string. The ‘1’ bits are sent by driving the data line high for 0.9us, followed by driving the line low for 0.35ns, The ‘0’ bits are sent by driving the line high for 0.35us, then driving it low for 0.90us. The frame is in 8-bit Green, 8-bit Red then 8-bit Blue format, and within each colour the MSB is sent first.