Hello FPGA lovers! Engineering traditional synth machines using development platforms like Arduino and FPGAs is becoming quite the trend now. Today’s post however takes a twist from the traditional synth machines where sounds are produced by either flicking switches or pressing buttons. The synth machine under discussion is a photosensitive synth machine which uses LDRs interfaced with FPGA in place of button switches and this gives an almost touch screen like feel to the device.
The Hardware required is a FPGA board (adaption may be required), 16 LDRs, 16 high value resistors, a speaker, adequate jumpers and 2 breadboards. The entire project has only 2 sets of hardware implementation off the FPGA board. A speaker is directly wired to the FPGA board besides 16 LDRs which function as the photosensitive keyboard. These LDRs work as a 16 bit Keyboard that inputs signals to the FPGA board to convert to sound signals. The connection diagrams and screen shots are given here.
The coding used for the project has been done in VHDL and the author has given the codes in different modules. The note decoder module on Step 2 is one of the most crucial modules in the whole code as it assigns a particular frequency for the 16 bit value from the LDR keyboard. The sound generator module on Step 4 is the next crucial module as it sends the respective frequency (pitch) values to the speaker interfaced with the FPGA.
Through this link you will find the ucf files for the project. This can be modified according to your convenience in case you would like to add more functionality like sustain buttons and other effects.
Hello FPGA enthusiasts! Today’s project takes you back to school where you learned the binary system. The author has designed a decimal to binary conversion game using FPGA. It is time to see if you did pay attention in class! The game uses a random number generator which generates any number between 0 and 255. Using the 8 switches on the FPGA, the player needs to guess the binary value right, following which the LEDs glow green. If you do go wrong, the LED matrix glows red showing you guessed incorrectly.
The FPGA board used for this project is the Nexys2 (you may need to adapt yours). It has an LED display, 8 switches and 8 LEDs which are perfectly suited for this project. Besides this some PMOD connectors, an 8×8 LED matrix, resistors, wires, daisy chain wires and 2 breadboards are the other hardware required. Steps 3, 4 and 5 of the project deals with understanding and connecting the hardware used for the project. Since the FPGA has a set of switches and a display, the extra hardware required is less for this project.
The programming language used by the author is VHDL. The program to run on the FPGA is available in step 9 as a zip file. The code has been broken down into modules for ease of understanding. Assigning the pins has been explained in detail in step 10, and the process of creating the bit file to run on the FPGA has been explained in step 11.
Hello FPGA innovators! Remember the arcade obstacle avoidance game where blocks of pixels fall on you and you steer clear of them moving left or right? Today’s project attempts to re engineer the same game using a VGA and FPGA. Here, a pseudo random code is used to generate obstacles that fall down and buttons on the FPGA are used to move the cursor so that none of the obstacles hit it.
The only hardware required to execute this project is an FPGA board (you might need to adapt yours if different from the author’s), a computer monitor and connection cables. This is because the FPGA board has inbuilt push buttons that can be used to move the cursor of the game, and also has the necessary DACs and VGA interfaces required to run the game.
The coding done by the author is in VHDL and everything starting from a functional flowchart to running the bit file for FPGA has been described from steps 1 to 9. Since the buttons on the FPGA has a bouncing issue, a separate debouncer code needs to be run which is available on step 2. Details regarding the VGA, coding for random obstacles and checking for collisions and updating the game are given from steps 3 to 7.
Though the authors put in 50+ hours of effort and made a great attempt, the game still could be done in a lot more simpler ways. The main code is available in the introduction to spare other followers from putting in more additional effort, but starting from choosing a different FPGA board to running through basics of other games implemented using VGA and FPGA can end up delivering something better with a lot less effort.
Greetings FPGA innovators! Ever had the problem of forgetting to switch off the room lights on your way out? Do you have frequent guests who are not as mindful as you when it comes to power saving? In today’s project we see how to build a simple gadget with the FPGA to switch off your room lights once there is no one in. Not only will The FPGA trip light save power and work intelligently, but it will also help you cut power costs.
The Hardware needed for the project are a FPGA board (adaptation to your own device might be required), 2 off IR transceiver pairs, 4 off 1000 ohm resistors, 2 off 33 ohm resistors and 2 off 100 ohm resistors besides 2 breadboards and jumper wires. The author has shared details regarding the circuit setup, the FPGA board and the Breadboard connections in step 4. A housing model for the circuit has been shown in step 5 which will help the circuit to be used in a more compact and practical way.
The FPGA has been coded with the VHDL language. The black box diagram for implementing in the FPGA and its descriptions has been given in detail in step 2. The code has been divided into modules and has been given for ready availability in step 3.
The basic operation of the gadget is such that one transceiver pair counts the number of people entering the room, and the other counts the number of people leaving the room. The FPGA acts as a simple comparator and when both the counts are equal, the room lights are turned off.
Hello FPGA enthusiasts! The FPGA is truly a tool that can stretch the horizon of possibility and in today’s project we will find out how an FPGAcan be used as an universal remote control. Ever had the problem of falling asleep while watching TV? Not anymore! The Universal Timed remote with FPGA is a timed remote which can be used to switch off any TV set once the timer ticks down!
The Hardware needed for this project are a FPGA Board, a breadboard, a 300 ohm resistor, male to male connecting wires and an IR LED and Sensor pair besides a TV set to test the device on. The circuit diagram has been given by the author in step 2.
The code has been written using VHDL and the VHDL setup for the FPGA is given in step 3. The code has been subdivided into modules and the whole file has also been attached in step 3 as a zip file. The main modules are the IR control and the Timer, which work in tandem to switch off the TV once the timer counts down.
Future enhancements and possible improvements have also been shared by the author. The timer can be set between 1 hour and 99 hours though it has been designed only to work for your own TV set. But a little bit of tweaking can make this a universal remote too!
Hello FPGA hobbyists! Ever wondered what it would be like to see sound? The author thveryat very same curiosity for close to 10 years, and kept a constant vigilance for ideas to build something that would help him materialize his dreams. The Daredevil camera, built using a bunch of MEMS microphones and a FPGA actually lets you see sound.
The author started the project wielding inspiration from the Duga RADAR. However, the scale of the project becomes huge and something beyond what hobbyists can afford. The author then tried a more practical but tedious and time consuming design approach which involved using an array of microphones. Each microphone in the array picks the sound relative to its position and displays it on screen, which will always be different from the next microphone because of the difference in position.
While the logic behind this is sound, implementing an array of microphones, each having a Pre-amp stage and then an ADC stage before feeding inputs to the FPGA is not practical. The cost and time put into the project becomes huge, and even then error margins can be significantly high.
This is the reason why the author used a set of MEMS microphones. MEMS microphones have an inbuilt Pre-amp and ADC stage, and thus the project collapses in complexity. All that is needed is an array of MEMS microphones and an FPGA board to implement the project. FPGAs are FFT friendly and this has a huge part in the project.
The author has shared the PCB design layout here. Besides this a number of fail safes such as spare patterns for a Flash chip, SOIC and DIP. He also used micro SD cards for each array to store the data and send it for processing to get an output of close to 30 frames per second. The FPGA, a great tool for pipelining is used to get his output.
The author then tried out the theory in an 8×8 array and arrived at the conclusions that the device is pretty sensitive as it even picks up sound way reflections from surfaces. But since anechoic chambers are impossible to build at home, he went on to build a 16×16 array.
While the results can be seen in this page, the author is yet to perfect his design. There are persistent issues with micro SD card since its storage algorithm conveniently cuts off data to compress data, which is essential for the FPGA to build a 30 Frame/sec output.
To be heard…or seen.
Greetings FPGA fans! Today’s post takes power generation and conservation to another level! We all know that Solar Panels are an excellent source of non-conventional power. But if the panel is not facing the sun the power generation is never optimum. The sun changes its position continuously and a static solar panel can only generate optimum power for a short window of time when it directly faces the sun. But what if the solar panel too changed its position with respect to the sun? Then we would have a case where the panel generates optimum power for more than 8 hours which is a lot more compared to just the 1-2 hours it does when it is static!
Today’s project aims at making a dynamic solar panel with FPGA. This Dynamic Solar Panel changes its position according to the Sun’s position by making use of a comparator that compares voltage values periodically and rotates the panel. The hardware required for this project are 2 Bidirectional Parallax servo motors, a 9V DC Solar Panel, a FPGA, a Breadboard, A 3D Printed frame and 3 100 Ohm resistors.
The Project basically involves the use of an FSM designed by the author. The design steps have been explained in detail from steps 2 – 8. Any FPGA with sufficient inputs and outputs can be used for this project but the code shared by the author has been programmed for the Basys 3. So unless you’re feeling really adventurous, it would be best to follow what the author has done!
The program has been done in VHDL (.vhd) and is available here. It has been arranged into different modules and each module corresponds to one of the design steps from 2 – 8. The program is pretty easy to follow and improvising it to suit another FPGA board should be easy if you know VHDL.
The wiring has been shared in step 10. The author has used a 3D printed frame whose schematic has been shared in step 11. However if you plan on building your own frame from wood or cardboard, you can refer the sketches.
Hi FPGA lovers! In our conquest to find studio quality sound, we stumbled upon the YM 2151 FM Synth Chip which has been used by Yamaha from time immemorial in a number of their electronic keyboards and arcade games. The YM 2151 has a Digital output rather than an analog output and this makes it ideal for further signal processing using DSP. However due to the absence of an on chip DAC, the YM 2151 needs a suitable DAC chip that does not add substantial noise while analog reconstruction.
Today’s post is a detailed study of the YM 2151 and its coupling with YM 3012 DAC which are almost like inseparable siblings of the Yamaha family. The YM 2151 is a 24 pin IC which gives a 16 bit output. The first 3 bits have no significant value, whereas the next 10 bits in order are the significant bits or mantissa and the last 3 bits are the exponents. The author has conducted a number of measures for a fixed value of supply voltage and has shared the results in his post.
The 3 parameters of concern are “d”, “n” and “m” which are the value of mantissa, exponent value and size of LSB respectively. The output voltage of the chip is given by a fixed relationship between these parameters where Vout= m*d + n.
From this result, the Verilog code for YM 3012 in the post starts making sense. The code has been designed around the fact that the base voltage is Vdd/2. However no explanation was given as to why this particular voltage was chosen. From this result, we deduce that Vdd/2 is the principle value because it supports maximum swing in positive and negative directions. This way the 10 bit resolution of the mantissa can be put to full use to produce the desired harmonic frequencies of high quality and clarity.
This is the reason why the YM 3012 DAC is best for this Synth chip, because it is essentially the second half of Yamaha’s FM Synth Chip design. The chip has been broken into two parts (the 2151 and 3012) to give the benefit of getting a 16 bit Digital output for further processing before reconstruction of the analog signal.
This makes the YM 2151 perfect for creating sound boards. The YM 2151 can be used in combination with a FPGA to recreate any themes. The FPGA adds a degree of flexibility in the chip’s output since the output of the YM 2151 is digital and can be easily processed by the FPGA.