Papilio One gets new features for the “Sump” Logic Analyzer project.

The Papilio Logic Analyzer project has finally caught up to the Openbench Logic Sniffer’s codebase. The same code, version 2.12, is running on both the Openbench Logic Sniffer and the Papilio One now. Head over to the Papilio Logic Analyzer project page to download the latest release and take advantage of the new features:

  • Dynamic memory allows 24K of sampling depth for 8 channels and 6K for 32 channels.
  • UART speed is 115200 instead of 38400.
  • New and greatly improved Java Client from Jawi.

 

  • Main window (light theme) with scope.
  • Main window (light theme) with measure tooltip.
  • Main window (dark theme).
  • Measurement tool.
  • OLS general settings.
  • OLS trigger settings.
  • General preferences.






Yet Another VGA VHDL project posted to Gadget Forge!

A new VHDL project that puts the new VGA Wing through its paces has been posted to Gadget Forge. The project is called “Yet Another VGA” controller and it allows cursors, a waveform, and text to be written anywhere on an 800×600 screen. Head over to the YAVGA project page and download the bitstreams to check it out right away and then download the source code and start hacking away.

 

While you are at Gadget Forge don’t forget to look around for other examples and project that can be used with the Open Source Papilio One FPGA development board.