Greetings FPGA lovers! Today’s post takes you into yet another interdisciplinary project that links pure mathematics, FPGA and VHDL to build something beautiful! The Mandelbrot set is a series of complex numbers that tend to infinity when operated upon by a special operator. These numbers when grouped together create a beautiful image sequence which might appear to be chaotic initially. But simplifying the set, we soon find that Mandelbrot’s numbers are nothing but fractals and this concept can be explored and understood visually with FPGA and VHDL.
Today’s project is an FPGA based Fractal explorer that has been built out of the Papilo Duo kit which includes Xilinx Spartan 6 LX9 FPGA, an ATmega 32U4 microcontroller and a 512 MB Static RAM. Some other hardware needed is a basic 7” LCD screen, a Joystick, a few buttons and a rotary encoder.
The colour map shown in the project is navigated by using the joystick to move around, rotary knob to chose colour scheme and the buttons to zoom in and out. These controls are connected to the ATmega 32U4 microcontroller which is interfaced with the FPGA through an SPI interface.
The LCD has been tweaked to display 800 x 600 and the FPGA has also been correspondingly set to process 800 x 600 pixel fractals using the inbuilt DSP 48s. The project is inspired by the Mandelbrot Fractal Generator by Hamster.
Though the code for this project is still unavailable at the moment, you can refer Hamster’s project to get the basic dataflow and code in the C language. Once you do have the logic at hand, the project can easily be converted to the FPGA/VHDL combination instead of the Computer/C combination used by Hamster.
The project is an excellent way to continue learning coding through VHDL and get used to the Papilo Duo Kit.
Hello FPGA lovers! FPGAs are versatile tools that can be used for research, analysis, engineering applications and entertainment. Today’s project falls into the last category! The nine shine LED game is an interactive game that tests your sense of timing. It consists of an array of LEDs that are turned on sequentially, and you need to press a button exactly when the central LED lights up to progress in the game. The game has been organised into 10 levels by the author with increasing difficulty based on speed to make it fun and challenging.
The project uses an FPGA along with an array of LEDs. The Hardware required for the project is an FPGA Board, USB-to-Micro cable, Eight LEDs, 8 resistors and a Big Dome Pushbutton. To fabricate the setup board for LEDs, the materials required are a wooden board rubber feet, soldering iron and solder, heat shrink, drill, drill bit, hole saw, hot glue gun and insulated electrical wire.
The coding has been done in VHDL and is available in modules in step 2. The author has explained what each module does and its significance in the FPGA system in this step. Right from the FSMs to the main module, the author has gone to great lengths in explaining the code even in fine aspects such as button debouncing issues.
Hello FPGA enthusiasts! Today’s project takes you back to school where you learned the binary system. The author has designed a decimal to binary conversion game using FPGA. It is time to see if you did pay attention in class! The game uses a random number generator which generates any number between 0 and 255. Using the 8 switches on the FPGA, the player needs to guess the binary value right, following which the LEDs glow green. If you do go wrong, the LED matrix glows red showing you guessed incorrectly.
The FPGA board used for this project is the Nexys2 (you may need to adapt yours). It has an LED display, 8 switches and 8 LEDs which are perfectly suited for this project. Besides this some PMOD connectors, an 8×8 LED matrix, resistors, wires, daisy chain wires and 2 breadboards are the other hardware required. Steps 3, 4 and 5 of the project deals with understanding and connecting the hardware used for the project. Since the FPGA has a set of switches and a display, the extra hardware required is less for this project.
The programming language used by the author is VHDL. The program to run on the FPGA is available in step 9 as a zip file. The code has been broken down into modules for ease of understanding. Assigning the pins has been explained in detail in step 10, and the process of creating the bit file to run on the FPGA has been explained in step 11.
Greetings FPGA innovators! Stepper motors can be an integral part of projects that have a dimension of mobility to them. Be it rovers, robots, drones or claw machines, controlling stepper motors with joysticks is an integral part and FPGAs accomplish speed control easily. Today’s post is about using a FPGA and a joystick to control stepper motors.
The Hardware required for the project is a FPGA board, 2 PmodSTEP drivers, 1 PmodJSTK, 2 Stepper motors, a USB A to B micro cable and 2 12 pin PMOD cables. Since the author is only focused on the control of the stepper motors, the hardware for this project is limited. However it can be expanded based upon the scale of your endeavour.
The code structure is given by the author in step 2. The author has configured the PmodJSTK interface to receive data and not send data to the LEDs on the board. The working principle is pretty simple, where the decoder works out the signals from the Joystick and sends it to the drivers in the form of electrical signals that make the motors turn left, right, stay still or maintain course. The FPGA acts as a simple interconnect between the drivers. The code has been given in a zip file by the author in step 3.
The coding language used is VHDL and the code is divided into modules. Step 4 has been dedicated to code generation and creation of the executable bit file that can be used on the FPGA. Step 5 illustrates the connections for the project.
Hello FPGA lovers! Today’s post is an interesting one which helps us visualize the audio spectrum with the help of your FPGA and an LED strip. Using a VGA cable, the spectrum can be visualised in a computer monitor as well. The microphone on theFPGA used (you may need to adapt this to your own board) captures the surrounding sounds and uses the FPGA to convert it into a perceivable visual output. The author has explained the principle of working in step 2. The input audio signal is stored in 2 block RAMs. The 1st RAM consists of the time domain representation which is used for display in the VGA. The 2nd RAM consists of the Frequency domain representation using FFT which is displayed both in the VGA and the LED strip.
The Hardware required for this project is a FPGA board, USB A to B micro cable, VGA cable, 30 LED Strip, VGA display (PC monitor) and 3 male to male jumper wires. The author has used the PC monitor as the VGA display for this project. However you can use a dedicated LCD screen or any other VGA display if you choose to. The hardware connections are explained in step 3.
The code is available as a zip file in step 4. The author has dedicated steps 4 and 5 towards installing and generating the program for the board. The language used is VHDL and the code has been broken down into modules. The zip file consists of the source files, a readme file explaining the code, a .tcl file to automatically build the project and the .bit and .bin files for programming the FPGA.
Greetings inhabitants of the FPGA world! Today’s post is about a project that can be a huge part of a number of other different projects that use FPGA as their core. Be it a claw machine or a drone or a navigator robot, interfacing Joysticks with FPGA will be a fundamental part of many of your future work. This article will help you control any device on a two dimensional platform with the code for movement in the XY plane. Moving in 3D (flight in the case of drones) can be easily achieved by using two joysticks in place of one.
The Author has wrapped up her project in a set of 5 steps to keep things short and sweet. The hardware needed for this project is simply a FPGA board, a system with Xilinx Vivado installed, Digilent PmodJSTK and a USB A to B micro cable. A general idea regarding the project is given in Step 2. The Joystick uses the SPI interface to receive and transmit data from and to the FPGA board.
The code for this project has been readily supplied in step 3 as a zip file. The contents can be sorted into a number of modules which have been coded in Vivado 2015.4. So using a different version of the software will mean you need to copy paste the codes into a new project file in your system.
The code can then be converted to bit stream to programme the board. You can also programme 2 joysticks (for Drones or RC Cars) since only the top bank of the PMOD Header in the FPGA board (you may need to adapt this to your own board) has been used for 1 joystick.
Hello FPGA hobbyists! Ever wondered what it would be like to see sound? The author thveryat very same curiosity for close to 10 years, and kept a constant vigilance for ideas to build something that would help him materialize his dreams. The Daredevil camera, built using a bunch of MEMS microphones and a FPGA actually lets you see sound.
The author started the project wielding inspiration from the Duga RADAR. However, the scale of the project becomes huge and something beyond what hobbyists can afford. The author then tried a more practical but tedious and time consuming design approach which involved using an array of microphones. Each microphone in the array picks the sound relative to its position and displays it on screen, which will always be different from the next microphone because of the difference in position.
While the logic behind this is sound, implementing an array of microphones, each having a Pre-amp stage and then an ADC stage before feeding inputs to the FPGA is not practical. The cost and time put into the project becomes huge, and even then error margins can be significantly high.
This is the reason why the author used a set of MEMS microphones. MEMS microphones have an inbuilt Pre-amp and ADC stage, and thus the project collapses in complexity. All that is needed is an array of MEMS microphones and an FPGA board to implement the project. FPGAs are FFT friendly and this has a huge part in the project.
The author has shared the PCB design layout here. Besides this a number of fail safes such as spare patterns for a Flash chip, SOIC and DIP. He also used micro SD cards for each array to store the data and send it for processing to get an output of close to 30 frames per second. The FPGA, a great tool for pipelining is used to get his output.
The author then tried out the theory in an 8×8 array and arrived at the conclusions that the device is pretty sensitive as it even picks up sound way reflections from surfaces. But since anechoic chambers are impossible to build at home, he went on to build a 16×16 array.
While the results can be seen in this page, the author is yet to perfect his design. There are persistent issues with micro SD card since its storage algorithm conveniently cuts off data to compress data, which is essential for the FPGA to build a 30 Frame/sec output.
To be heard…or seen.
Greetings FPGA fans! Today’s post takes power generation and conservation to another level! We all know that Solar Panels are an excellent source of non-conventional power. But if the panel is not facing the sun the power generation is never optimum. The sun changes its position continuously and a static solar panel can only generate optimum power for a short window of time when it directly faces the sun. But what if the solar panel too changed its position with respect to the sun? Then we would have a case where the panel generates optimum power for more than 8 hours which is a lot more compared to just the 1-2 hours it does when it is static!
Today’s project aims at making a dynamic solar panel with FPGA. This Dynamic Solar Panel changes its position according to the Sun’s position by making use of a comparator that compares voltage values periodically and rotates the panel. The hardware required for this project are 2 Bidirectional Parallax servo motors, a 9V DC Solar Panel, a FPGA, a Breadboard, A 3D Printed frame and 3 100 Ohm resistors.
The Project basically involves the use of an FSM designed by the author. The design steps have been explained in detail from steps 2 – 8. Any FPGA with sufficient inputs and outputs can be used for this project but the code shared by the author has been programmed for the Basys 3. So unless you’re feeling really adventurous, it would be best to follow what the author has done!
The program has been done in VHDL (.vhd) and is available here. It has been arranged into different modules and each module corresponds to one of the design steps from 2 – 8. The program is pretty easy to follow and improvising it to suit another FPGA board should be easy if you know VHDL.
The wiring has been shared in step 10. The author has used a 3D printed frame whose schematic has been shared in step 11. However if you plan on building your own frame from wood or cardboard, you can refer the sketches.