OpenBench Logic Sniffer 3.07 “Demon” Core Release!

Download the OpenBench Logic Sniffer 3.07 “Demon” core Release from the new Logic Sniffer information portal.

 

There has been a lot of new progress with the OpenBench Logic Sniffer. “Dogsbody” has contributed an exciting new Verilog core that adds some significant improvements:

 

3.07 OpenBench Logic Sniffer Release

  • 3.07 FPGA “Demon” Core
    • Fix for 200Mhz sampling in “Demon” Core
  • 3.0 PIC Firmware
    • SPI speed increase
    • Fix for Winbond read issue
  • 0.9.3 SP1 Jawi OLS client
    • Bug fixes

 

3.06 FPGA “Demon” Core Release

  • RLE works correctly for all memory depths.
  • HP 16550a Advanced triggering mode. (The client does not support this yet, but the Verilog core supports triggers just like the HP 16550a!)
  • Meta tags inside the FPGA core allow the client to determine the version running on FPGA.
  • Jawi’s client “0.9.3.1” fixes RLE issues, adds JTAG decoder, and 1-Wire decoder.
  • Version 2.6 of the PIC firmware increases SPI transfer speed. The difference is noticeable, this release is named “Demon” because it is a speed demon.
  • OLS Upgrader works for both Windows and Linux now. A simple menu based GUI steps you through upgrading your OLS.

  • Main window (light theme) with scope.
  • Main window (light theme) with measure tooltip.
  • Main window (dark theme).
  • Measurement tool.
  • OLS general settings.
  • OLS trigger settings.
  • General preferences.

 

 

 

 

 

OpenBench Logic Sniffer 3.06 “Demon” Core Test Release!

Download the OpenBench Logic Sniffer 3.06 “Demon” core Test Release.

 

There has been a lot of new progress with the OpenBench Logic Sniffer. “Dogsbody” has contributed an exciting new Verilog core that adds some significant improvements:

  • RLE works correctly for all memory depths.
  • HP 16550a Advanced triggering mode. (The client does not support this yet, but the Verilog core supports triggers just like the HP 16550a!)
  • Meta tags inside the FPGA core allow the client to determine the version running on FPGA.
  • Jawi’s client “0.9.3.1” fixes RLE issues, adds JTAG decoder, and 1-Wire decoder.
  • Version 2.6 of the PIC firmware increases SPI transfer speed. The difference is noticeable, this release is named “Demon” because it is a speed demon.
  • OLS Upgrader works for both Windows and Linux now. A simple menu based GUI steps you through upgrading your OLS.

  • OLS Upgrader
  • Main window (light theme) with scope.
  • Main window (light theme) with measure tooltip.
  • Main window (dark theme).
  • Measurement tool.
  • OLS general settings.
  • OLS trigger settings.
  • General preferences.

 

 

 

 

 

How-to debug internal FPGA Logic with the $50 Openbench Logic Sniffer.

This tutorial shows how to use the $50 OpenBench Logic Sniffer to debug internal FPGA logic. Debugging internal FPGA logic can be pretty challenging and time consuming, a lot can be done using simulation but when you have logic that interacts with the outside world debugging can come to a grinding halt. The traditional solution is to use the $500+ Chipscope Pro software, but for many this is just too expensive. This tutorial shows a cheap and effective way to get a look at what is going on inside your FPGA.

 

The FPGA development board used in the screencast is Gadget Factories Open Source Papilio One board. Think of the Papilio One as the “Arduino” of FPGA development boards.

 

Part 1

Introduction, overview, and background information.

Continue reading “How-to debug internal FPGA Logic with the $50 Openbench Logic Sniffer.”

Version 2.12a of the OpenBench Logic Sniffer Windows Installer released.

A new Windows installer for the OpenBench Logic Sniffer (OLS)  is now available for download. This installer greatly simplifies the initial task of getting the OLS up and running.

Download OpenBenchLogicSniffer-2.12a-Setup.exe

Features of the new installer are:

  • Installs the original Sump Java client and Jawi’s excellent alternative Logic Sniffer client.
  • Automatically installs the Windows Device Drivers for the OLS.
  • Places shortcuts on the Start Menu to Documentation, User Guide, and Tutorial Videos.
  • Includes a menu based OLS upgrader that streamlines the upgrade process.

Calling all VHDL hackers, we can use help on the OLS project.

In order to try to foster a fun environment where people can come and help us hack away at the Sump Logic Analyzer code we have recorded a screencast for one of the outstanding tracker items we have.

We are trying to create a single bitstream that can dynamically change its memory configuration based on the channel groups that are selected in the client. Currently the end user has to load one bitstream to select 8 channels with a memory depth of 24K and another bitstream for 32 channels with 6K samples. We want to make it as simple as deselecting memory groups.

Discussions about this item can be found in the DP Forum.

The tracker item for this issue can be accessed on the OLS project homepage.