This tutorial shows how to use the $50 OpenBench Logic Sniffer to debug internal FPGA logic. Debugging internal FPGA logic can be pretty challenging and time consuming, a lot can be done using simulation but when you have logic that interacts with the outside world debugging can come to a grinding halt. The traditional solution is to use the $500+ Chipscope Pro software, but for many this is just too expensive. This tutorial shows a cheap and effective way to get a look at what is going on inside your FPGA.
The FPGA development board used in the screencast is Gadget Factories Open Source Papilio One board. Think of the Papilio One as the “Arduino” of FPGA development boards.
Introduction, overview, and background information.
In order to try to foster a fun environment where people can come and help us hack away at the Sump Logic Analyzer code we have recorded a screencast for one of the outstanding tracker items we have.
We are trying to create a single bitstream that can dynamically change its memory configuration based on the channel groups that are selected in the client. Currently the end user has to load one bitstream to select 8 channels with a memory depth of 24K and another bitstream for 32 channels with 6K samples. We want to make it as simple as deselecting memory groups.