How-to debug internal FPGA Logic with the $50 Openbench Logic Sniffer.

This tutorial shows how to use the $50 OpenBench Logic Sniffer to debug internal FPGA logic. Debugging internal FPGA logic can be pretty challenging and time consuming, a lot can be done using simulation but when you have logic that interacts with the outside world debugging can come to a grinding halt. The traditional solution is to use the $500+ Chipscope Pro software, but for many this is just too expensive. This tutorial shows a cheap and effective way to get a look at what is going on inside your FPGA.

 

The FPGA development board used in the screencast is Gadget Factories Open Source Papilio One board. Think of the Papilio One as the “Arduino” of FPGA development boards.

 

Part 1

Introduction, overview, and background information.

Continue reading “How-to debug internal FPGA Logic with the $50 Openbench Logic Sniffer.”

Calling all VHDL hackers, we can use help on the OLS project.

In order to try to foster a fun environment where people can come and help us hack away at the Sump Logic Analyzer code we have recorded a screencast for one of the outstanding tracker items we have.

We are trying to create a single bitstream that can dynamically change its memory configuration based on the channel groups that are selected in the client. Currently the end user has to load one bitstream to select 8 channels with a memory depth of 24K and another bitstream for 32 channels with 6K samples. We want to make it as simple as deselecting memory groups.

Discussions about this item can be found in the DP Forum.

The tracker item for this issue can be accessed on the OLS project homepage.

Video Overview of Sump Logic Analyzer VHDL Code.

This is a four part video overview of the Sump Logic Analyzer VHDL Code that is used with the OpenBench Logic Sniffer project. The OLS is a joint project between Dangerous Prototypes and Gadget Factory, it can be purchased for $50.

This series of videos is meant to help people who want to start developing for the Sump project get a feel for the layout.


PART 1:

Continue reading “Video Overview of Sump Logic Analyzer VHDL Code.”