Hey everyone! Today we got a very interesting project for you, our forum user Hamster has started a forum topic to share with us his new project. He designed a Virtual Logic Analyser for the Papilio One that could be used on any Xilinx FPGA where you can gain access to one spare I/O pin.
Hamster wanted to make something similar to Xilinx’s Virtual Logic Analyzer “ChipScope” that would allow him to inspect what is going on within his projects and he decided to design his own Virtual Logic Analyser “CheapScope”.
In the past I’ve been playing around with RS232 and found it quick and simple to use from both the interface from both the FPGA design and the client software, so I sketched out a design and over a couple of nights CheepScope was born!
CheepScope is functional but limited and it has these features:[checklist]
- 16 channels
- 1024 samples
- Requires only one I/O pin – or no pins if your Dev board has a USB to RS232 interface
- Light on resources – one Block RAM and about 100 slices.
Check out the CheapScope wiki page here to read the whole thing complete with source code, exemples, etc…
Feel free to discuss in the forum thread.
Thanks for sharing your project with us Hamster!