By way of forum user Icebear comes word that a new debugger is on the horizon which should work on the Papilio:
Many developers got used to this: Plug in a JTAG connector to your embedded target and debug the misbehaviour down to the hardware. No longer a luxury, isn’t it?
When you move on to a soft core from opencores.org for a simple SoC solution on FPGA, it may be. Most of them don’t have a TAP – a Test Access Port – like other off the shelf ARM cores.
We had pimped a ZPU soft core with in circuit emulation features a while ago (In Circuit Emulation for the ZPU). This enabled us to connect to a hardware ZPU core with the GNU debugger like we would attach to the emulator. The same has been implemented for the ADI Blackfin family for a long time.
Coming across various MIPS compatible IP cores without debug facilities, the urge came up to create a standard test access port that would work on this architecture as well. There is an existing Debug standard called EJTAG, but it turned out way more complex to implement than simple In Circuit Emulation (ICE) using the above TAP from the ZPU.
So we would like to do the same as with the ZPU:
» Compile programs with the -elf-gcc
» Download programs into the FPGA hardware using GDB
» set breakpoints, inspect and manipulate values and registers, etc.
» Run a little “chip scope”
This is pretty cool news for anyone who has been wanting debug ability that works on the Papilio, and more information should be coming shortly from Embedded World 2013 in Nueremberg, so mark your calendars for February!
(via Tech Section 5)