By way of Colin O’Flynn over at NewAE, we’ve got a wonderful video showing how to basically exploit the Xilinx HLS (High-Level Synthesis) in Vivado to make your own FIR filter in only about 25 minutes! I could attempt to write a synopsis of what is covered in the video, but as they say – a video is worth 10,000 words. It is a bit long, but if you’ve got the patience for it you might walk away with a couple of new tricks up your sleeve!
Vivado – it’s Xilinx’s new design tool system. Part of this is the ‘High Level Synthesis’ option – something you can also get it seems for ~$2k. I’m using these design tools in the “wrong” way, in that I’m generating HDL & then synthesizing it with the normal ISE chain. Some of the parts I’m using aren’t officially supported in Vivado it seems. Plus I’m currently more used to the ISE design flow, so don’t want to throw everything away.
After you watch the video, don’t forget to click on over to Colin’s site at NewAE to check out the full scoop.
- Xilinx High Level Synthesis – original article (NewAE)