Xilinx provides a free PCI Express core “EndPoint Block Plus” and free Wizard to Configure it with their free version of Xilinx-ISE WebPack.
So Open Xilinx Core Generator and select End Point Plus
Presently core is inactive, we need to make it active first , On Menu Select File -> New Project to create project and select a FPGA (if we are using Dragon-E so we select Virtex-5 otherwise whatever FPGA you are using select the same)
From Generation tab you can select language, either you want to develop your project in Verilog or VHDL etc.
Now the “EndPoint Block Plus” core becomes active and you can double-click on it to start the wizard.
On the first page, name your component. Here we chose “my_endpoint_blk_plus”. The rest is ok for Dragon-E, so click Next >
Now we can modify the Vendor/Device IDs
And we can also define or update address spaces
By Clicking Next > will get some least bothered Menu items, so we can click on “Generate” to generate the core and its documentation.
After clicking Generate we will get the bit file , Now we can program our FPGA to Generate real PCI Express Traffic.