after a few years being forced to play with other targets, I revisited the Papilio One and ported my in-house ‘MaSoCist’ setup to it. Yet another solution, you might think. Well, the motivation was to go minimal, but configureable. The MaSoCist is different in that respect that it rather is an environment than an actual design, however it is powered by the resource-saving ZPU architecture by default. The original Zealot ZPU variant, enhanced with a bit of debug logic, is doing an ok job for configuration, but is wasting quite a few cycles on the dual port RAM I/O and had shortcomings on the interrupt handling side, so I had bashed out a pipelined variant which does things a little differently. It’s been in use as configuration processor or even test bench for more complex logic so far. Logic usage is a little higher than the original Zealot. The full SoC with UART, PWM, Timer, IRQ controller, and simple Cache logic for virtual adressing of a SPI flash takes less than 50% of the Papilio One.
Currently, the CPU is running at 32 MHz only. There’s more in for it, if the memory system and fetch logic is improved (v2, in the making). The v0 and v1 variant of the core run on a three-stage pipeline.
Anyhow, I managed to upload a (crappy) video, moving pictures speak more: