XC6BP – FPGA ‘Bus Pirate’

Here is an interesting project that we somehow missed. It’s an FPGA based clone of the Dangerous Prototypes Bus Pirate. Looks cool, would love to get this running on the Papilio FPGA.


A FPGA based design with a soft CPU and USB device interface implemented in Verilog.
This design uses an OpenRISC compatible CPU (my AltOR32 implementation) running at 48MHz (a convenient speed for USB) and features cut-down USB 1.1 (Full Speed), SPI and GPIO interfaces.

via Ultra-Embedded

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