Hello FPGA lovers! Today’s post is an interesting one which helps us visualize the audio spectrum with the help of your FPGA and an LED strip. Using a VGA cable, the spectrum can be visualised in a computer monitor as well. The microphone on theFPGA used (you may need to adapt this to your own board) captures the surrounding sounds and uses the FPGA to convert it into a perceivable visual output. The author has explained the principle of working in step 2. The input audio signal is stored in 2 block RAMs. The 1st RAM consists of the time domain representation which is used for display in the VGA. The 2nd RAM consists of the Frequency domain representation using FFT which is displayed both in the VGA and the LED strip.
The Hardware required for this project is a FPGA board, USB A to B micro cable, VGA cable, 30 LED Strip, VGA display (PC monitor) and 3 male to male jumper wires. The author has used the PC monitor as the VGA display for this project. However you can use a dedicated LCD screen or any other VGA display if you choose to. The hardware connections are explained in step 3.
The code is available as a zip file in step 4. The author has dedicated steps 4 and 5 towards installing and generating the program for the board. The language used is VHDL and the code has been broken down into modules. The zip file consists of the source files, a readme file explaining the code, a .tcl file to automatically build the project and the .bit and .bin files for programming the FPGA.
Greetings FPGA innovators! Ever had the problem of forgetting to switch off the room lights on your way out? Do you have frequent guests who are not as mindful as you when it comes to power saving? In today’s project we see how to build a simple gadget with the FPGA to switch off your room lights once there is no one in. Not only will The FPGA trip light save power and work intelligently, but it will also help you cut power costs.
The Hardware needed for the project are a FPGA board (adaptation to your own device might be required), 2 off IR transceiver pairs, 4 off 1000 ohm resistors, 2 off 33 ohm resistors and 2 off 100 ohm resistors besides 2 breadboards and jumper wires. The author has shared details regarding the circuit setup, the FPGA board and the Breadboard connections in step 4. A housing model for the circuit has been shown in step 5 which will help the circuit to be used in a more compact and practical way.
The FPGA has been coded with the VHDL language. The black box diagram for implementing in the FPGA and its descriptions has been given in detail in step 2. The code has been divided into modules and has been given for ready availability in step 3.
The basic operation of the gadget is such that one transceiver pair counts the number of people entering the room, and the other counts the number of people leaving the room. The FPGA acts as a simple comparator and when both the counts are equal, the room lights are turned off.
Hello FPGA enthusiasts! The FPGA is truly a tool that can stretch the horizon of possibility and in today’s project we will find out how an FPGAcan be used as an universal remote control. Ever had the problem of falling asleep while watching TV? Not anymore! The Universal Timed remote with FPGA is a timed remote which can be used to switch off any TV set once the timer ticks down!
The Hardware needed for this project are a FPGA Board, a breadboard, a 300 ohm resistor, male to male connecting wires and an IR LED and Sensor pair besides a TV set to test the device on. The circuit diagram has been given by the author in step 2.
The code has been written using VHDL and the VHDL setup for the FPGA is given in step 3. The code has been subdivided into modules and the whole file has also been attached in step 3 as a zip file. The main modules are the IR control and the Timer, which work in tandem to switch off the TV once the timer counts down.
Future enhancements and possible improvements have also been shared by the author. The timer can be set between 1 hour and 99 hours though it has been designed only to work for your own TV set. But a little bit of tweaking can make this a universal remote too!
Greetings FPGA fans! Today’s post takes power generation and conservation to another level! We all know that Solar Panels are an excellent source of non-conventional power. But if the panel is not facing the sun the power generation is never optimum. The sun changes its position continuously and a static solar panel can only generate optimum power for a short window of time when it directly faces the sun. But what if the solar panel too changed its position with respect to the sun? Then we would have a case where the panel generates optimum power for more than 8 hours which is a lot more compared to just the 1-2 hours it does when it is static!
Today’s project aims at making a dynamic solar panel with FPGA. This Dynamic Solar Panel changes its position according to the Sun’s position by making use of a comparator that compares voltage values periodically and rotates the panel. The hardware required for this project are 2 Bidirectional Parallax servo motors, a 9V DC Solar Panel, a FPGA, a Breadboard, A 3D Printed frame and 3 100 Ohm resistors.
The Project basically involves the use of an FSM designed by the author. The design steps have been explained in detail from steps 2 – 8. Any FPGA with sufficient inputs and outputs can be used for this project but the code shared by the author has been programmed for the Basys 3. So unless you’re feeling really adventurous, it would be best to follow what the author has done!
The program has been done in VHDL (.vhd) and is available here. It has been arranged into different modules and each module corresponds to one of the design steps from 2 – 8. The program is pretty easy to follow and improvising it to suit another FPGA board should be easy if you know VHDL.
The wiring has been shared in step 10. The author has used a 3D printed frame whose schematic has been shared in step 11. However if you plan on building your own frame from wood or cardboard, you can refer the sketches.
Greetings FPGA lovers! Today’s post is about building your own mini computer using FPGA. The project has been inspired by the first SSEM, popularly called the Manchester baby. The project resembles its inspiration in certain aspects, but being a homemade CPU with minimal components and coding, the specs are not as formidable as the SSEM.
The author has used a standard FPGA Papilo one 500k board, an 8×8 LED strip and a set of switches. The system has been designed for a total RAM of 64 bits, and the LED strip shows the RAM configuration every time data is entered at a new address. Besides this, the author has also used a rechargeable battery, charging circuit, clipper circuit to avoid excess voltage and a number of peripheral ICs.
The coding followed for FPGA is based on simple VHDL (.vhd) and being an open source project, the author has shared all VHDL code here. The CPU is programmed directly using the address and data switches. A number of values can be stored just by setting the CPU on the User mode and entering data to the addresses of the 64 bit RAM.
The system also has an adjustable clock which helps while simulating and running the code in variable clock speeds. The author has successfully demonstrated through the video that the CPU can work as a Random number Generator (from 1 to 6) and a pendulum. Besides this the CPU can also be connected to external components like an array of LEDs for clarity of output.
Though the FPGA basedC88 Homebrew CPU has limited RAM and storage capabilities, it is still a great start to create experimental modules and platforms using FPGA that can host a number of applications.
Hello FPGA enthusiasts! Today’s project takes sound production using FPGA to another level. The project under focus is building an electric keyboard/composer using FPGA. The keyboard acts as a song tune composer where a network of switches on the FPGA board is connected in precedence such that while a switch is on, the corresponding note plays.
The major hardware components needed are just a FPGAboard (you may need to adapt this project to your own board), a speaker capable of playing a wide range of frequencies, and not just a monotone, and an auxiliary cable or suitable wires for connecting the speaker to the FPGA board.
The coding has been done using Xilinx ISE in the VHDL (.vhd). The author has given a detailed pin assignment as well as a basic VHDL background explanation. The code has been shared from step 5 to 9 and each module has been well explained by the author. The modules basically consist of a frequency division for playing different frequencies of sound and process statements for fixing parameters like precedence and sensitivity.
Setting the port map and executing the program has been explained in steps 10 and 11. By switching different switches you get different tones, though combinational tones cannot be made since precedence is followed.
Hi there FPGA lovers! Here we have another release of our series of YM2151 posts.
To recreate the YM 2151 in FPGA using VHDL, every aspect of the YM 2151 needs to be mapped on to the recreation platform. However an interesting aspect regarding the YM 2151 is that it uses random values for generation of noise (in Spanish) sound outputs like shocks, explosions and other disruptive sounds. While a general range of the signals used to generate this noise can be sampled, the YM 2151 has close to 18 bits for random signal generation which leads to a total of 218 signals.
The YM 2151 however uses a Linear Feedback Shift Register for this random sequence generation, and this considerably narrows down the possibility from more than a hundred thousand samples to a very narrow range. The output noise sequence can be predicted because of the feedback element, as every feedback signal can only have one selected output.
The MAME Source code for the emulator consists of a code for generating noise. This code has been used by the author to share a set of 256 samples. Though the samples appear to be seemingly random at first, a definitive pattern can be decoded from the samples depending upon the feedback given.
The Berlekamp- Massey Algorithm was used by the author to conclude that a definite relationship exists between the feedback and generated sequence for all bits except 0 and 4, contrary to the assumed 0 and 8 in the beginning. However the fact that the outputs after 0 and 4 cannot be predicted leads to the fact that there might be more than 218 samples. Thus from a set of more than hundred thousand random signals to generate noise in the YM 2151, the author has narrowed down the possibility to a handful of feedback signals which can be used to create the clone of YM 2151 in Verilog for FPGA.
Hello FPGA lovers! Today’s post is about making real studio quality music rather than the monotone buzzers from conventional circuits. FPGAs can be used to create monotone sounds such as beeps by using the right combination of DACs and buzzers. However these devices cannot be used to create studio quality sound that not only plays over a harmonic range of frequencies but also sounds professional to hear. The YM 2151 FM Synth chip is one chip that can be coupled with the FPGA to create great sound and even tweak it to an extent by using the YM 2151- FPGA combination for driving the chip.
The Project in focus is the sound board of the arcade version of the popular game Double Dragon. The schematic for this project has been given by the author in the first post. The YM 2151 is a chip that outputs digital data, and as a result a DAC chip will be necessary before coupling the output to a speaker.
However, this digital output is a blessing in disguise since the output from the IC can be filtered for noise, adjusted for pitch variations and converted to almost any desired form with the FPGA. A Papilio Plus FPGA Board, a bread board, jumper wires, Arcade Mega Shield for Interfacing, PS2 Keyboard Controller, VGA Controller, Hexy module and the YM 2151 are the main hardware components you will need for this project besides a few other peripherals seen in the schematic.
The coding follows conventional VHDL (.vhd) for the Papilo FPGA that can be executed in Xilinx or similar software. The code execution has been explained in detail in the second post in the thread along with 3 screenshots that shows the code execution and necessary plots. The code is available towards the end of the article.