OpenBench Logic Sniffer 3.06 “Demon” Core Test Release!

Download the OpenBench Logic Sniffer 3.06 “Demon” core Test Release.


There has been a lot of new progress with the OpenBench Logic Sniffer. “Dogsbody” has contributed an exciting new Verilog core that adds some significant improvements:

  • RLE works correctly for all memory depths.
  • HP 16550a Advanced triggering mode. (The client does not support this yet, but the Verilog core supports triggers just like the HP 16550a!)
  • Meta tags inside the FPGA core allow the client to determine the version running on FPGA.
  • Jawi’s client “” fixes RLE issues, adds JTAG decoder, and 1-Wire decoder.
  • Version 2.6 of the PIC firmware increases SPI transfer speed. The difference is noticeable, this release is named “Demon” because it is a speed demon.
  • OLS Upgrader works for both Windows and Linux now. A simple menu based GUI steps you through upgrading your OLS.

  • OLS Upgrader
  • Main window (light theme) with scope.
  • Main window (light theme) with measure tooltip.
  • Main window (dark theme).
  • Measurement tool.
  • OLS general settings.
  • OLS trigger settings.
  • General preferences.






Logic Sniffer Test Release 2.12 – Dynamic Memory Depth

A little while back we posted a call for help with the OpenBench Logic Sniffer project. The challenge was to add dynamic memory depth to the OpenBench Logic Sniffer VHDL code. Jochem Govers stepped up to the plate and submitted an excellent patch that does the job perfectly! As a prize for answering the challenge we sent Jochem a brand new Openbench Logic Sniffer!


Here is a screencast demonstrating the new functionality:

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