Phew,
Still working on revision 2.0 of the USB and S3E boards and the Butterfly Platform specification. It’s taking way longer then I was thinking it would.
On a side note, I looked through the Logic Analyzer source code and commented out the XON/XOFF code that is most likely limiting the speed to 38400. Next step is to re-synthesize the Logic Analyzer design at 115000 and do some testing.
Jack.
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