Cray-1 Supercomputer Recreated On FPGA

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FPGA Cray 1-A (left) and the original Cray-1 supercomputer (right)

Self-described “computational necromancer” Chris Fenton lives up to this description given his penchant for recreating classic computer hardware using FPGAs. With the assistance of the original design documents, reference manuals, and the like Chris recreated the iconic 1976 Cray-1 supercomputer on a Xilinx Spartan-3E 1600 development board. To complete the package Chris and his wife even built and painted a 1/10 scale-model enclosure for the FPGA Cray-1!

Now, let’s get down to specs – What is this bad boy running? The original machine ran at a blistering 80 MHz, and could use from 256-4096 kilowords (32 megabytes!) of memory. It has 12 independent, fully-pipelined execution units, and with the help of clever programming, can peak at 3 floating-point operations per cycle.

It’s a fairly RISC-y design, with 8 64-bit scalar (S) registers , 8 64-bit/64-word vector (V) registers, and 8 24-bit address (A) registers. Rather than a traditional cache, it uses a ‘software-managed’ cache with an additional 64 64-bit words (T registers) and 64 24-bit words (B registers). There are instructions to transfer data between memory and registers, and then register-to-register ‘compute’ instructions.

All the code for the Cray 1-x project is hosted on Google Code here if you’d like to give it a shot, or just take a look.  Come on, who wouldn’t want their own Cray supercomputer?!?

The original project page is here.

(via ChrisFenton.com)

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