In-Fabric Serialization: 1080p DVI-D With a Spartan 6 LX FPGA

The SERDES2 function in the Spartan 6 LX family of FPGAs can transmit at about 1Gb/s. This is a quite useful and respectable figure, and quite a few development boards combine this ability with the ability to generate TMDS (transition-minimized differential signaling) signals to implement a DVI-D / HDMI interface at next-to-no extra cost. For users of these boards, this is a great feature — being able to display 24-bit full color images is very appealing compared with the not-so-nice 8-bit or 12-bit analogue VGA (video graphics array) interface implemented on most older boards.

If you’re like me, you too would be slightly disappointed if you were to read the infamous XAPP495 application note to discover that 1Gb/s is only 66 percent of the bit rate required for a “Full HD” 1080p/60Hz display. My laptop can do 1080p, my $99 media player too, but not my FPGA board?

Using two 375MHz clocks, my technique implements 4:1 serialization and can generate a 1.5Gb/s stream of bits — fast enough to implement a full 1920×1080 @ 60Hz DVI-D interface without any extra hardware! It is also somewhat scalable — with three clocks, for example, the same technique can implement 6:1 serialization.