SDRAM Controller

Here is a very interesting Xilinx App note that includes full VHDL code for interfacing to a SDRAM chip. I’ve been meaning to see if this could be adapted as an example for the Papilio Pro, but never seem to find the time…

This document describes the VHDL design for interfacing CoolRunner™-II CPLDs with low power Mobile SDRAM memory devices. Mobile SDRAM is the ideal memory solution for wireless, handheld, and mobile computing applications, making this a perfect match with the Xilinx CoolRunner-II low power CPLD family.

via www.xilinx.com