How To Implement The Old Oberon System On A Modern FPGA

In today´s article we bring you an experiment carried out by Niklaus Wirth, a master of the Computer Science World. But this article goes beyond itself. It is much more than that because it is the introduction chapter for a thorough guide on how to implement the Oberon system, developed in the late 80´s on a modern FPGA.

The Oberon system was first created as a programming language to help academics teach system programming on a more simplified way. Later, in 1990 the Oberon Operating System was born. However, both the language and the operating system targeted a today-disappeared processor. Thus the main challenge was finding a modern processor that met the requirements. There was none, so let´s forget about this re-born Oberon thing…No! Mr. Wirth decided to take advantage of modern FPGA´s and build his own processor. This allowed him to also design both the hardware and the software. The chosen one, a Xilinx FPGA, made it possible to keep the design similar to the original one.

This new processor was called RISC and it´s been implemented on a low-cost Digilent Spartan-3 dev board, so it´s cheap for schools to get sets of kits of them. The only hardware added that is different from the first design, were a mouse interface and a SD card (instead of the hard-disk drive). All the details and files can be found here.

The Oberon operating system has a core that includes a memory allocator with a garbage collector and a file system together with a loader, a text system, a text editor and a viewer system. It is to highlight that system initialization only takes about 2 seconds.

The Oberon compiler is hosted on the system itself and it uses the top-down recursive-descent parsing method.

At this point, you might have thought: “Ok. This Oberon system uses its own programming language and it has been implemented on a Xilinx FPGA, which I know does not support Oberon…How did they do it?”

Well, fair enough and right to the point. The hardware-description language (HDL) used for the Oberon system was called Lola. The first thought was to adapt Lola to Xilinx FPGA´s, however complexity and proprietary issues were enough to rule out the idea. Instead, a detour was taken. Lola needed to be translated to a language for which Xilinx provided a synthesis tool. Verilog was selected. For this translation to take place Lola needed to be parsed, then translated and then parsed again. After reformulating all the modules of RISC5 (the Verilog module name for the RISC processor) in Lola, Lola-2 was born.

Finally, it´s worth remarking one of the great advantages of this system. You can safely build upon it and not being afraid of hidden characteristics such as back doors, not even on the hardware. This at the same time makes the integrity of the system very robust against attacks.

This system is a proof of how much can be achieved with just a little.

Read the full article and if you want to know more about this great project for teachers and learners, simply click here.

By Niklaus Wirth