Use Your FPGA To Build A Password Cracker!

Here we have a project developed by a German guy who wanted to get a 100 EUR device that could do 10 million key guesses per second.

The main point of this design is to use multiple crypt cores in order to reduce the time needed to crack a UNIX Crypt. A modified DES algorithm is used. It´s interesting to highlight that employing a multiple-crypt-cores approach allows scale better to the available amount of logic on smaller devices, which are the most-spread kind of unit for a regular user.

In this work, the FPGA implemented was a XILINX XC3S1000-4. Due to an expected high power consumption, an external power supply needed to be added together with a couple of heat sinks. All the information about the required add-ons can be found here.

The code that runs is implemented using VHDL. You can download the VHDL Crypt Implementation following this link.

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Having said that…Enjoy!

By M.Poppitz