Papilio One
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Tutorial: Custom AVR8 Soft Processor for use with Arduino IDE. (V1.2)
This screencast provides instructions for downloading and synthesizing a custom AVR8 soft processor for use with a version of the Arduino IDE that has been modified for use with the Papilio. Prerequisites: AVR8 Source Code Arduino IDE modified for the Papilio. Xilinx ISE free “Webpack” version. Part 1: Downloading the AVR8 source code. Selecting only…
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ZPUino Alpha 2 is available.
Alvaro has released Alpha 2 of the ZPUino. The ZPUino project makes a powerful, 32-bit, 100Mhz, ZPU processor available for the Papilio hardware. The best part is that your sketches will still run on the ZPUino! If you haven’t seen the ZPUino project yet take a look.
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Papilio.cc: All Papilio information just a click away.
The new Papilio.cc information portal is an easy to navigate website that puts all Papilio information just a couple clicks away.
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Papilio One FPGA pin to Wing connector.
This maps out the FPGA pin numbers to their Wing locations. Contributed by user Thelonious PDF Version
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New Project Staging area added with Papilio Synth project.
In the spirit of fostering more community involvement we created a New Project Staging page were we will stage and work on our upcoming projects. As we work on new projects we will make an announcement on Twitter and in the IRC channel. All work will be staged in SVN in this new project page…
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Papilio One gets new features for the “Sump” Logic Analyzer project.
The Papilio Logic Analyzer project has finally caught up to the Openbench Logic Sniffer’s codebase. The same code, version 2.12, is running on both the Openbench Logic Sniffer and the Papilio One now. Head over to the Papilio Logic Analyzer project page to download the latest release and take advantage of the new features: Dynamic…
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Yet Another VGA VHDL project posted to Gadget Forge!
A new VHDL project that puts the new VGA Wing through its paces has been posted to Gadget Forge. The project is called “Yet Another VGA” controller and it allows cursors, a waveform, and text to be written anywhere on an 800×600 screen. Head over to the YAVGA project page and download the bitstreams to…
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How-to debug internal FPGA Logic with the $50 Openbench Logic Sniffer.
This tutorial shows how to use the $50 OpenBench Logic Sniffer to debug internal FPGA logic. Debugging internal FPGA logic can be pretty challenging and time consuming, a lot can be done using simulation but when you have logic that interacts with the outside world debugging can come to a grinding halt. The traditional solution…
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