Papilio user Matthew Hagerty put together a very nice implementation of a simple SDRAM controller for the Papilio Pro FPGA. Written in VHDL, it sacrifices some speed for ease of use and simplicity. After all, not every project needs to use the full capacity of the SDRAM chip.
You can read about his epic adventure learning the ins and outs of SDRAM, simulating his code, and finally running on hardware in this forum thread.
It can be a lonely task working on something like this, so we wanted to congratulate Mathew and give a big virtual high five for his awesome work!