Xilinx App Note: Writing Efficient Testbenches



I’ve been looking through Xilinx App Notes recently and came across some great information to share on the blog. This app note gives lots of great background information that will help you in writing test benches to provide stimulus for your HDL code so you can perform simulation before you ever load a design to the Papilio.


Testbenches are the primary means of verifying HDL designs. This application note provides guidelines for laying out and constructing efficient testbenches. It also provides an algorithm to develop a self-checking testbench for any design.




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