Here is another new language for high level hardware description. We haven’t used it but this article has a clear description of why a hardware description language that goes further then VHDL or Verilog is needed.
Cx (formerly C~) is a new language for hardware design and verification that is at an intermediate level of abstraction between RTL and HLS. Why is a new language necessary? Because most hardware designers are still stuck with RTL, and because today’s High-Level Synthesis (HLS) does not live up to its promises. Register Transfer Level (RTL) is pretty self-explanatory — you think in terms of registers and how data flows from one register to the next. This closely matches what happens physically, which is another way of saying that it is a very thin layer of abstraction. In turn, this means that you spend a lot of time dealing with implementation-level details that would not concern you if you were working at a higher level of abstraction. VHDL and Verilog are the two main historical languages for describing RTL designs. Both date back to the 1980s and — in the grand scheme of things — have seen little evolution since then. Recent efforts to improve on these two relics include open-source initiatives like MyHDL (RTL in Python) and Chisel (RTL in Scala). MyHDL is led by Jan Decaluwe, while Chisel was created at UC Berkeley with the goal of facilitating processor design. At the other end of the spectrum, we have HLS. We can think of today’s HLS as your manager’s solution. It was sold to her or him (at a premium) as a way to increase productivity and obtain the same performance as RTL. The problem is that […]