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  • OpenBench Logic Sniffer 3.07 “Demon” Core Release!

    Download the OpenBench Logic Sniffer 3.07 “Demon” core Release from the new Logic Sniffer information portal.   There has been a lot of new progress with the OpenBench Logic Sniffer. “Dogsbody” has contributed an exciting new Verilog core that adds some significant improvements:   3.07 OpenBench Logic Sniffer Release 3.07 FPGA “Demon” Core Fix for…

    Jack Gassett

    March 2, 2011
    Logic Sniffer
    OLS, Software Release
  • Papilio One FPGA pin to Wing connector.

    This maps out the FPGA pin numbers to their Wing locations. Contributed by user Thelonious PDF Version

    Jack Gassett

    February 25, 2011
    Papilio
    Papilio One
  • OpenBench Logic Sniffer 3.06 “Demon” Core Test Release!

    Download the OpenBench Logic Sniffer 3.06 “Demon” core Test Release.   There has been a lot of new progress with the OpenBench Logic Sniffer. “Dogsbody” has contributed an exciting new Verilog core that adds some significant improvements: RLE works correctly for all memory depths. HP 16550a Advanced triggering mode. (The client does not support this…

    Jack Gassett

    February 8, 2011
    Logic Sniffer
    OLS, Software Release, Test Release
  • New Project Staging area added with Papilio Synth project.

    In the spirit of fostering more community involvement we created a New Project Staging page were we will stage and work on our upcoming projects. As we work on new projects we will make an announcement on Twitter and in the IRC channel. All work will be staged in SVN in this new project page…

    Jack Gassett

    February 4, 2011
    Papilio
    Papilio One
  • Papilio One gets new features for the “Sump” Logic Analyzer project.

    The Papilio Logic Analyzer project has finally caught up to the Openbench Logic Sniffer’s codebase. The same code, version 2.12, is running on both the Openbench Logic Sniffer and the Papilio One now. Head over to the Papilio Logic Analyzer project page to download the latest release and take advantage of the new features: Dynamic…

    Jack Gassett

    February 4, 2011
    Papilio
    Gadget Forge Example Project, Papilio One, Software Release
  • Yet Another VGA VHDL project posted to Gadget Forge!

    A new VHDL project that puts the new VGA Wing through its paces has been posted to Gadget Forge. The project is called “Yet Another VGA” controller and it allows cursors, a waveform, and text to be written anywhere on an 800×600 screen. Head over to the YAVGA project page and download the bitstreams to…

    Jack Gassett

    January 31, 2011
    Papilio
    Gadget Forge Example Project, Papilio One, Software Release, VHDL
  • Gadget Factory IRC channel on Freenode.

    Gadget Factory is starting an IRC channel on Freenode, feel free to stop by and say hello! The IRC channel is hosted on www.freenode.net and is named #GadgetFactory. The chat room can be accessed online with Freenodes webchat page.

    Jack Gassett

    January 28, 2011
    Uncategorized
  • How-to debug internal FPGA Logic with the $50 Openbench Logic Sniffer.

    This tutorial shows how to use the $50 OpenBench Logic Sniffer to debug internal FPGA logic. Debugging internal FPGA logic can be pretty challenging and time consuming, a lot can be done using simulation but when you have logic that interacts with the outside world debugging can come to a grinding halt. The traditional solution…

    Jack Gassett

    January 26, 2011
    Logic Sniffer
    ISE Webpack Tutorial, OLS, olsvids, Papilio One, Tutorial, VHDL Tutorial, video
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